The present invention relates to a shift register. More particularly, the present invention is directed to a MIS dynamic shift register which can be composed using a small number of circuit elements.
For example, in a MIS dynamic memory device, the so called auto-refresh operation for refreshing data stored in each memory cell is effected by memorizing the number of a word line to be refreshed in the memory device, and by incrementing the number of the word line and refreshing the memory cells connected to each word line. In Japanese Patent Application No. 58-115887 filed on June 29, 1983 by the present applicant, there is disclosed a memory device which comprises a shift register, disposed parallel to a row decoder and in which a selecting signal for a word line to be refreshed is generated by using the output signal of the shift register, thereby sequentially selecting a word line to be refreshed. The shift register used in such a memory device is characterized in that, among all the bits thereof, the output of only one bit is "1" and the outputs of all the other bits are "0". By using the output of only one "1" bit, only one target word line is selected. It is also necessary that the width of one circuit stage on a semiconductor substrate of the shift register be not larger than the pitch length of the word lines. Generally, since the pitch length of the word lines is very narrow, it is necessary that the structure of each circuit stage of the shift register be very simple and the number of circuit components used therein be small.
In a conventional shift register which can memorize and transmit data having any pattern, each circuit stage has a very complex circuit structure and a large number of circuit components. Therefore, the circuit width of each circuit stage on a semiconductor device is relatively large, and it is impossible to use the shift register in the above-mentioned memory device.